There is a continuing goal in semiconductor processing to fabricate smaller and denser circuits. Correspondingly, the individual circuit components continue to be placed closer and closer together. Individual circuit elements or groups of elements are typically connected together by conductive lInes running over the substrate. Conductive lines within a given layer, as well as conductive lines in different layers, are typically electrically isolated from one another by dielectric materials commonly referred to as dielectrics.
Insulating dielectric materials exhibit a property known as a dielectric constant. Such is effectively a measurement of capacitance between two spaced conductors. The ratio of the capacitance between two conductors within a given material between them to the capacitance of the same two conductors with nothing (a vacuum) between them is known as the dielectric constant of the given material. Thus, a material with a high dielectric constant placed between two conductors increases the capacitance between the conductors. Where such materials would be highly desirable as capacitor dielectrics in capacitor constructions, such materials are highly undesirable as insulating material between conductors. Unneeded capacitance between conductive lines slows and otherwise adversely affects circuit performance.
Silicon dioxide has typically been a preferred interlevel dielectric layer material of choice. Although such material has a high dielectric constant, the prior art spacing between conductive components has been sufficiently great from one another to result in acceptable circuit designs. Yet as circuit density increases, and thus the spacing between adjacent devices decreases, there is a continuing goal to find and develop improved low dielectric constant materials for use as interlevel dielectrics. Such materials can, however, have their own associated drawbacks with respect to fabrication.
For example, one general class of low dielectric constant materials desirable for interlevel dielectrics are organic insulating materials such as parylene and polytetrafluoroethylene. Materials such as these have been shown to have very low dielectric constants of 2.0 or less, and are stable under high moisture and high temperature conditions. However, it is difficult to pattern vias into these materials utilizing photoresist as the photoresist cannot be readily stripped off selectively from these materials. The organic nature of photoresist and the organic insulating dielectric layer materials would make selective stripping of the two very difficult, as best.
One proposed technique which does enable utilization of these low dielectric constant materials and photoresist includes enlarging the contact area where the contact is to be made. For example, consider a series of spaced conductive lines formed at the same substantial level relative to a semiconductor substrate, and having organic insulating dielectric layer material therebetween. Consider also a silicon dioxide layer overlying both the conductive lines and organic insulating dielectric layer material, and through which a contact opening utilizing photoresist is to be made to one of the conductive lines. If the contact opening to the line is slightly misaligned such that the organic insulator is also exposed, etching of the silicon dioxide selectively relative to both the conductive line and organic material can be conducted such that disastrous over-etch will not occur. Yet, subsequent photoresist strip will undesirably also result in etching of the organic insulating dielectric material exposed within the contact opening. Such could result in destruction of the circuit. Such can be prevented by enlarging of the contact area of the line to which the contact opening is to be etched to avoid exposure of the organic material upon mask misalignment of a certain degree. However, this is at the expense of consuming precious wafer real estate.
Accordingly, a need remains to develop improved techniques utilizing photoresist in etchings involving organic dielectric layer materials. Although the invention spawned from this concern, the artisan will appreciate applicability of the invention in other semiconductor processing areas, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.